論文
公開件数:153件
No. 種別 査読の有無 標題 単著・共著区分 著者 誌名 巻号頁 出版日 ISSN DOI URL
1 一般論文

83nJ/bit Transmitter Using Code-Modulated Synchronized-OOK on 65nm SOTB for Normally-Off Wireless Sensor Networks
共著
Van-Trung NGUYEN, Ryo ISHIKAWA, Koichiro ISHIBASHI
IEICE Transactions on Electronics
2018/ E101.C, 472-479
2018/07



2 一般論文

Diode Characteristics of a Super-Steep Subthreshold Slope PN-Body Tied SOI-FET for Energy Harvesting Applications

Takayuki Mori ; Jiro Ida ; Shun Momose ; Kenji Itoh ; Koichiro Ishibashi ; Yasuo Arai
IEEE Journal of the Electron Devices Society
2018/ vol6, 565-570
2018/06/01



3 一般論文

Field evaluation of an infectious disease/fever screening radar system during the 2017 dengue fever outbreak in hanoi, vietnam: a preliminary report

Guanghao Sun, Nguyen Vu Trung, Takemi Matsui, Koichiro Ishibashi, Tetsuo Kirimoto, Hiroki Furukawa, Le Thi Hoi, Nguyen Nguyen Huyen, Quynh Nguyen, Shigeto Abe, Yukiya Hakozaki
Journal of Infection
75/6, 593-595
2017/10/24



4 一般論文

A Small-Size Energy-Harvesting Electric Power Sensor for Implementing Existing Electrical Appliances into HEMS

Tsunoda, Y.; Tsuchiya, C.; Segawa, Y.; Sawaya, H.; Hasegawa, M.; Ishigaki, S.; Ishibashi, K.
IEEE Sersors J.
Vol.16/ No. 2, 457-463
2016



5 一般論文

A 1.36μW 312-315MHz Synchronized-OOK Receiver for Wireless Sensor Networks Using 65nm SOTB CMOS Technology

Minh-Thien Hoang, Nobuyuki Sugii, Koichiro Ishibashi
Elsevier Solid-State Elecronics
Vol 117, 161-169
2016



6 一般論文

A Study on Ultra-low Power and High Sensitibity CMOS RF Receiver for Wireless Sensor Networks
単著
Hoang Minh Thien

2015
2015



7 一般論文

A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode

Koichiro ISHIBASHI, Nobuyuki SUGII, Shiro KAMOHARA, Kimiyoshi USAMI, Hideharu AMANO, Kazutoshi KOBAYASHI, Cong-Kha PHAM
IEICE TRANSACTIONS on Electronics
Vol.E98-C/ No.7, 536-543
2015/07/01



8 一般論文

A 27.6 μW 315 MHz low-complexity OOK receiver with on-off RF front-end

Minh-Thien Hoang, Nobuyuki Sugii, Koichiro Ishibashi
IEICE Electronics Express
Vol. 12/ No. 7, pp. 20150206-
2015/05



9 一般論文

Speed enhancement at Vdd = 0.4 V and random τpd variability reduction and analyisis of τpd variability of silicon on thin buried oxide circuits

H.Makiyama, Y.Yamamoto, H.Shinohara, T.Iwamatsu, H.Oda, N.Sugii, K.Ishibashi, Y.Yamaguchi
Jpn. J. Appl. Phys.
vol.53
2014



10 一般論文

Ultralow-power SOTB CMOS Technology Operating Down to 0.4 V
共著
N.Sugii, Y.Yamamoto, H.Makiyama, T.Yamashita, H.Oda, S.Kamohara, Y.Yamaguchi, K.Ishibashi, T.Mizutani, T.Hiramoto
J. Low Power Electron. Appl.
4/ 2, 65-76
2014/04/24



11 一般論文

On-Chip
Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems

J. Kim, T. Nakura, K. Ishibashi, M. Ikeda and K. Asada
IEICE Trans. on Electronics
vol. E96-C/ no. 4, pp. 560-567
2013/04



12 一般論文

On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant

J. Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda and K. Asada
IEICE Trans. on Electronics
vol. E95-C/ no. 4, pp. 643-650
2012/04



13 一般論文

A low-power wide-range clock synchronizer with predictive-delay-adjustment scheme for continuous voltage scaling in DVFS control

M. Onouchi, Y. Kanno, M. Saen, S. Komatsu, Y. Yasu, and K. Ishibashi
IEEE Journal of Solid-State Circuits
vol45/ 11, 2312-2320
2010/11



14 一般論文

Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias

Y. Komatsu, K. Ishibashi, M. Nagata
IEICE TRANSACTIONS on Electronics
Vol.E90-C/ No.4, p.p.692-698
2007



15 一般論文

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, T. Yoshihara, M. Igarashi, M. Takeuchi, K. Kawashima, Y. Yamaguchi, K. Tsukamoto, M. Inuishi, H. Makino, K. Ishibashi, H. Shinohara
IEEE Journal of Solid-State Circuits
Vol. 42, p.p.820 - 829
2007



16 一般論文

Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias

Y. Komatsu, K. Ishibashi, M. Nagata
IEICE TRANSACTIONS on Electronics
E90-C/ 4, 692-698
2007/04



17 一般論文

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, T. Yoshihara, M. Igarashi, M. Takeuchi, K. Kawashima, Y. Yamaguchi, K. Tsukamoto, M. Inuishi, H. Makino, K. Ishibashi, H. Shinohara
IEEE Journal of Solid-State Circuits
vol42/ 4, 820-829
2007/04



18 一般論文

Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond

Y. Komatsu, Y. Arima, and K. Ishibashi
IEICE TRANSACTIONS on Electronics
Vol.E89-C/ No.3, pp.384-391
2006



19 一般論文

Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond

Y. Komatsu, Y. Arima, and K. Ishibashi
IEICE TRANSACTIONS on Electronics
E89-C/ 3, 384-391
2006/03



20 一般論文

An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs

T. Tsukada, Y.Hashimoto, K.Sakata, H.Okada, K.Ishibashi
IEEE Journal of Solid-State Circuits
vol. 40, pp. 67 - 79
2005/01



21 一般論文

CPU消費電力削減のための周波数-電圧協調型電力制御方式の設計ルールとフィードバック予測方式による適用

十山圭介、三坂智、相坂一夫、在塚俊之、内山邦男、石橋孝一郎、川口博、桜井貴康
電子情報通信学会論文誌 D-I
Vol.J87-D-I/ No.4, pp.452-461
2004



22 一般論文

0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme

Masanao Yamaoka, Kenichi Osada, Koichiro Ishibashi
IEEE Journal of Solid-State Circuits
vol. 39, pp. 934 - 940
2004/06



23 一般論文

3-D device modeling for SRAM soft-error immunity and tolerance analysis

Ken Yamaguchi, Yoshiaki Takemura, Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saito
IEEE Trans. Electron Devices
Vol. 51/ 2004., pp. 378 - 388
2004/03



24 一般論文

16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors

Kenichi Osada, Yoshikazu Saitoh, Eishi Ibe, Koichiro Ishibashi
IEEE Journal of Solid-State Circuits
vol. 38, pp. 1952 - 1957
2003/11



25 一般論文

Failure analysis of 6T SRAM on low-voltage and high-frequency operation

Shuji Ikeda, Yasuko Yoshida, Koichiro Ishibashi, Yasuhiro Mitsui
IEEE Trans. Electron Devices
Vol. 50, pp. 1270 - 1276
2003/05



26 一般論文

Threshold voltage-related soft error degradation in a TFT SRAM cell

Shuji Ikeda, Yasuko Yoshida, Shiro Kamohara, Koichi Imato, Koichro Ishibashi, Kazuo Takahashi
IEEE Trans. Electron Devices
Vol. 50., pp. 391 - 396
2003/02



27 一般論文

A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit

S. Shukuri, K. Ishibashi, K. Norisue, M. Yamaoka, K. Yanagisawa
IEEE Journal of Solid-State Circuits
Volume: 37/ Issue: 5, Page(s) : 599 -604
2002/05



28 一般論文

A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias

M. Miyazaki, G. Ono and K. Ishibashi
IEEE Journal of Solid-State Circuits
Volume: 37/ Issue: 2, Page(s) : 210 -217
2002/02



29 一般論文

CMOS Process Compatible ie-Flash (Inverse Gate Electrode Flash) Technology for System-on-a Chip

Shoji SHUKURI Kazumasa YANAGISAWA Koichiro ISHIBASHI
IEICE TRANSACTIONS on Electronics
Vol.E84-C/ No.6, pp.734-739
2001



30 一般論文

Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell

16.K. Osada, Luke Shin Jinuk; M. Khan, Y. Liou, K. Wang, K. Shoji, K. Kuroda, S. Ikeda and K. Ishibashi
IEEE Journal of Solid-State Circuits
Volume: 36/ Issue: 11, Page(s) : 1738 -1744
2001/11



31 一般論文

A 2-ns Access, 285-MHz, Two-port Cache Macro using Double Global Bit-Line Pairs

K. Osada, H. Higuchi, K. Ishibashi, N. Hashimoto, and K. Shiozawa
IEICE Transactions on Electronics
E83-C, 109-114
2000



32 一般論文

低電力システムクロック発生回路向け並列位相比較型ディレーロックドループ

宮崎祐行 石橋孝一郎
電子情報通信学会論文誌C
Vol.J83-C/ No.6, p.p. 502-508
2000



33 一般論文

An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode

H. Mizuno, K. Ishibashi, T. Shimura, T. Hattori, S. Narita, K. Shiozawa, S . Ikeda and K.Uchiyama
IEEE Journal of Solid-State Circuits
34.11, 1492-1500
1999



34 一般論文

A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio

H. Mizuno and K. Ishibashi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
(7,1), 139-144
1999



35 一般論文

A 6.93um2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory

M. Minami, N. OhkiH. Ishida, T. Yamanaka, A. Shimizu, K. Ishibashi, A. Satoh, T. Kure, T. Nishida, and T. Nagano
IEICE Transactions on Electronics
E80-C, 590-596
1997



36 一般論文

A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators

H. Mizuno, N. Matsuzaki, K. Osada, T. Shinbo, N. Ohki, H. Ishida, K . Ishibashi and T.Kure
IEEE Journal of SOLID-STATE CIRCUITS
(31.11, 1618-1624
1996



37 一般論文

An 8-mW, 8-kB Cache Memory Using an Automatic-Power-Save Architecture for Low Power RISC Microprocessors

Y. Shimazaki, K. Norisue, K. Ishibashi, and H. Maejima
IEICE Transactions on Electronics
E79-C, 1693-1698
1996



38 一般論文

A stacked split word-line (SSW) cell for low-voltage operation, large capacity, high speed SRAMs

Shuji Ikeda, Kyoichiro Asayama, Naotaka Hashimoto, Eri Fujita, Yasuko Yoshida, Atsuyosi Koike, Toshiaki Yamanaka, Koichiro Ishibashi, Satoshi Meguro
IEDM Tech. Dig.
pp. 809 - 812
1993/12



39 招待論文

A 910nW Delta Sigma Modulator using 65nm SOTB Technology for
Mixed Signal IC of IoT Applications,

Ishibashi Koichiro, Kikuchi Junya ,Sugii Nobuyuki
ICICDT2017
Session F
2017/05/23



40 招待論文

低電圧・低電力LSI技術の最新動向

石橋孝一郎
電子情報通信学会和文論文誌
Vol.J97-C/ No.1
2014/01



41 招待論文

Ultralow-Voltage
Operation SOTB
Technology toward
Energy Efficient
Electronics

N. Sugii, T. Iwamatsu, Y.
Yamamoto, H. Makiyama,
H. Shinohara, H. Od1, S.
Kamohara, Y. Yamaguchi,
T. Mizutani, K. Ishibashi
and T. Hiramoto
International Solid-State Devices and Materials
International Solid-State Devices and Materials
2013/09



42 招待論文

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond

K. Ishibashi, T. Fujimoto, T. Yamashita, H. Okada, Y. Arima, Y. Hashimoto, K. Sakata, I. Minematsu, Y. Itoh, H. Toda, M. Ichihashi, Y. Komatsu, M. Hagiwara, and T. Tsukada
IEICE Transactions on Electronics
E89-C/ 3, 250-262
2006/03



43 招待論文

Analog Circuit Design Methodology in a Low Power RISC Microprocessor

K. Ishibashi, H. Higuchi, T. Shimbo, K. Uchiyama, K. Shiozawa, N. Hashimoto, and S. Ikeda
IEICE Transactions on Electronics
E81-A, 210-217. 3
1998



44 招待論文

High-speed CMOS SRAM Technologies for Cache Applications

K. Ishibashi
IEICE Transactions on Electronics
E79-C, 724-734
1996



45 国際会議プロシーディングス等

First Experimental Confirmation of Ultralow Voltage Rectification by Super Steep Subthreshold Slope “PN-Body Tied SOI-FET” for High Efficiency RF Energy Harvesting and Ultralow Voltage Sensing
共著
S. Momose, J. Ida1, T. Yamada1, T. Mori1, K. Itoh1, K. Ishibashi and Y. Arai
IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFEREN C E
2018, 10.4-
2018/10/15



46 国際会議プロシーディングス等

"A 375 nA Input Off Current Schmitt Triger LDO for Energy
Harvesting IoT Sensors"

Koichiro Ishibashi ; Shiho Takahashi
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
2018, 187-190
2018/07/09



47 国際会議プロシーディングス等

Energy-Aware Receiver-Driven Medium Access Control Protocol for Wireless Energy-Harvesting Sensor Networks
共著
Ryo Tanabe and Tatsuhiro Kawaguchi, ; Ryohei Takitoge and Koichiro Ishibashi; Koji Ishibashi
IEEE Consumer Communications & Networking Conference
*/ *
2018/01/12



48 国際会議プロシーディングス等

Implementation of Condition-Aware Receiver-Initiated MAC Protocol to Realize Energy-Harvesting Wireless Sensor Networks,
共著
Tatsuhiro Kawaguchi, Ryo Tanabe, Ryohei Takitoge, Koichiro Ishibashi and Koji Ishibashi
IEEE Consumer Communications & Networking Conference
*/ *
2018/01/12



49 国際会議プロシーディングス等

LOW-POWER ENHANCED TEMPERATURE BEAT SENSOR WITH LONGER COMMUNICATION DISTANCE
BY DATA-RECOVERY ALGORITHM

Ryohei Takitoge, Masataka Kishi, Koichiro Ishibashi
IEEE SENSORS2017
IEEE SENSORS 2017, 379-381
2017/10/29



50 国際会議プロシーディングス等

Gate Controlled Diode Characteristics of Super Steep Subthreshold Slope PNBody
Tied SOI-FET for High Efficiency RF Energy Harvesting

S. Momose, J. Ida, T. Mori1, T. Yoshida1, J. Iwata1, T. Horii1, T. Furuta1, K. Itoh1, K.Ishibashi
S3S Conferrence2017
S3S Conferrence/ 2017
2017/10/16



51 国際会議プロシーディングス等

A 0.148nJ/conversion 65nm SOTB Temperature Sensor LSI Using ThermistorDefined
Current Source

Shinya Nii, Koichiro Ishibashi

S3SConference/ 2017
2017/10/16



52 国際会議プロシーディングス等

DC Current Beat: Wireless and Non-Invasive DC Current Sensing Scheme
共著
Koichiro Ishibashi , Makoto Serizawa, Ryohei Takitoge, Shohei Ishigaki , Tsuyoshi Ishige
MDPI journals
1/ 4, 567-567
2017/09/24



53 国際会議プロシーディングス等

Power Beat and Temperature Beat Sensors
— Precise, Low Cost, and Energy Harvesting Sensing Scheme for IoT Applications —

Koichiro ISHIBASHI, Ryohei TAKITOGE, Shohei ISHIGAKI

VJMW2017
2017/06/13



54 国際会議プロシーディングス等

Review of Steep Subthreshold Slope Devices and its possibility for
High Efficiency RF Energy Harvesting

Jiro IDA,Kenji ITOH, Koichiro ISHIBASHI

VJMW2017
2017/06/13



55 国際会議プロシーディングス等

SOTB Technology, which Enables Perpetually Reliable CPU for IoT Applications

K. Ishibashi, N. Sugii, K. Kobayashi, T. Koide, H. Nagatomi and S. Kamohara
Fourth Berkeley Symposium on Energy Efficient Electronic Systems
\DOI: 10.1109/E3S, 1-3
2015



56 国際会議プロシーディングス等

A 400mV 0.59mW Low-power CAM-based Pattern Matching System on 65nm SOTB Process

Duc-Hung Le, Nobuyuki Sugii, Shiro Kamohara, Hong-Thu Nguyen, Koichiro Ishibashi, Cong-Kha Pham
TENCON 2015
TENCON 2015
2015/11/01



57 国際会議プロシーディングス等

Designs of Ultra-Low-Power and Ultra-Low-Leakage
65nm-SOTB LSI for IoT Applications

Koichiro Isibashi
IEEE S3S Conference 2015
IEEE S3S Conference 2015
2015/10/05



58 国際会議プロシーディングス等

Power Beat: A Low‐cost and Energy Harvesting Wireless Electric Power Sensing Scheme for BEMS

Shohei Ishigaki and Koichiro Ishibashi
ICBEST2015
ICBEST2015
2015/08/31



59 国際会議プロシーディングス等

Design of a Low-power Fixed-point 16-bit Digital Signal
Processor Using 65nm SOTB Process

Le, Duc-Hung; Sugii, Nobuyuki; Kamohara, Shiro; Nguyen,
Xuan-Thuan; Ishibashi, Koichiro; Pham, Cong-Kha
2015 IEEE International Conference on Integrated Circuit Design and Technology
Design and Technology
2015/06



60 国際会議プロシーディングス等

Perpetuum-Mobile Sensor Network Systems using a CPU on 65nm SOTB CMOS Technology

Koichiro Ishibashi, Cong-Kha Pham, Nobuyuki Sugii

ICDV 2014
2014



61 国際会議プロシーディングス等

Low Power Channel Scanning with Contiki's IPv6 Stack for Wireless Sensor Network

Tran Ngoc Thinh, Tu Nguyen, Bui Van Hiev, Koichiro Ishibashi
ACOMP2014
ACOMP2014
2014/11/20



62 国際会議プロシーディングス等

A 0.75V 0.574mW 2.16GHz - 3.2GHz Differential Multipass
Ring Oscillator on 65nm SOTB CMOS Technology

Minh-Thien Hoang, Nobuyuki Sugii,
Koichiro Ishibashi
ICDV 2014
ICDV 2014
2014/11/14



63 国際会議プロシーディングス等

A CARD SIZE ENERGY HARVESTING ELECTRIC POWER SENSOR FOR IMPLEMENTING EXISTING ELECTRIC APPLIANCES INTO HEMS

Yuki Tsunoda, Chikara Tsuchiya, Yuji Segawa, Hajime Sawaya, Minoru Hasegawa, Koichiro Ishibashi
IEEE SENSORS 2014
IEEE SENSORS 2014
2014/11/02



64 国際会議プロシーディングス等

Design of a Low-power Fixed-point 16-bit Digital Signal Processor Using 65nm SOTB Process

Duc-Hung Le, N. Sugii, S. Kamohara, H. Oda, K. Ishibashi, Cong-Kha Pham
IEEE Region 10 ATC 2014
IEEE Region 10 ATC 2014
2014/10



65 国際会議プロシーディングス等

A 36nA Thermal Run-away Immune VBB Generator Using Dynamic Substrate Controlled Charge Pump for Ultra Low Sleep Current Logic on 65nm

H. Nagatomi, N. Sugii, S. Kamohara, K. Ishibashi
2014 IEEE S3S Conference
2014 IEEE S3S Conference
2014/10/07



66 国際会議プロシーディングス等

A 53μW -82dBm Sensitivity 920MHz OOK Receiver Design Using Bias Switch Technique on 65nm SOTB CMOS Technology

H.M. Thien, N. Sugii, K. Ishibashi
2014 IEEE S3S Conference
2014 IEEE S3S Conference
2014/10/07



67 国際会議プロシーディングス等

A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode

S. Kamohara, N. Sugii, K. Ishibashi, K. Usami,
H. Amano4, K. Kobayashi5, and Cong-Kha Pham
Hot Chips 2014
Hot Chips 2014
2014/08



68 国際会議プロシーディングス等

Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy Efficient Electronics in IoT Era

S. Kamohara, N. Sugii, Y. Yamamoto, H. Makiyama, T. Yamashita, T. Hasegawa, S. Okanishi, H. Yanagita, M. Kadoshima, K. Maekawa, H. Mitani, Y. Yamagata, H. Oda, Y. Yamaguchi, K. Ishibashi, H. Amano, K. Usami, K. Kobayashi, T. Mizutani, T. Hiramoto, Low-power Electronics Association & Project
2014 Symposia on VLSI Technology and Circuits
2014 Symposia on VLSI Technolo
2014/06/12



69 国際会議プロシーディングス等

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA Sleep Current using Reverse Body Bias Assisted 65nm SOTB CMOS Technology

Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham, Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Shiro Kamohara, Masaru Kadoshima, Keiichi Maekawa, Tomohiro Yamashita, Duc-Hung Le, Takumu Yomogita, Masaru Kudo, Kuniaki Kitamori, Shuya Kondo, Yuuki Manzawa
Cool Chips XVII
Cool Chips XVII
2014/04/16



70 国際会議プロシーディングス等

A Challenge to Perpetuum Computing using SOTB Technology

Koichiro Ishibashi
ACOMP 2013
ACOMP 2013
2013



71 国際会議プロシーディングス等

An ultra-low power LNA design using SOTB CMOS devices

Hoang Minh Thien, Koichiro Ishibashi
2013 Thailand-Japan Micro Wave 2013
2013 Thailand-Japan Micro Wave
2013/12



72 国際会議プロシーディングス等

Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by P/N Control with Back for Ultralow 0 4 Operation

H.Makiyama, Y. Yamamoto, H. Shinohara, T. Iwamatsu, H. Oda, N. Sugii, K. Ishibashi, T. Mizutani, T. Hiramoto, Y. Yamaguchi
2013 IEDM Technica Program
2013 IEDM Technica Program
2013/12



73 国際会議プロシーディングス等

A 4pA/Gate Sleep Current 65nm SOTB Logic Gates Using
On-chip VBB Generator for Energy Harvesting Sensor
Network Systems

Hiroki Nagatomi, Le Duc-Hung,
Cong-Kha Pham, Nobuyuki Sugii,
Shirou Kamohara, Toshiaki
Iwamatsu and Koichiro Ishibashi
ICDV 2013
ICDV 2013
2013/11



74 国際会議プロシーディングス等

A 44NW/10MHz Minimum Power Operation of 50K Logic Gate using 65nm SOTB Devices
with Back Gate Control

S. Morohashi, N. Sugii, T. Iwamatsu, S. Kamohara, Y. Kato, C-K. Pham1 and K. Ishibashi;
1The University of Electro Communications, Japan, 2Low-Power Electronics Association & Project
PAGE 19
2013 SOI-3DI Subthreshold Microelectronics Technology Unified Conference
2013 SOI-3DI Subthreshold Micr
2013/10



75 国際会議プロシーディングス等

Vmin=0.4 V LSIs are the real with Silicon-on-Thin-Buried-Oxide (SOTB) —
How is the application with "Perpetuum-Mobile" micro-controller with SOTB?

N. Sugii, T. Iwamatsu, Y. Yamamoto, H. Makiyama, H. Shinohara, H. Oda, S. Kamohara,
Y. Yamaguchi, K. Ishibashi, T. Mizutani, and T. Hiramoto
IEEE S3S Conference 2013
IEEE S3S Conference 2013
2013/10



76 国際会議プロシーディングス等

Speed Enhancement at
Vdd = 0.4 V and Randam
τpd Variability Reduction
of Silicon on Thin Buried
Oxide (SOTB)

H. Makiyama, Y.
Yamamoto, H. Shinohara,
T. Iwamatsu, H. Oda, N.
Sugii, K. Ishibashi and Y.
Yamaguchi
International Solid-State Devices and Materials
International Solid-State Devi
2013/09



77 国際会議プロシーディングス等

Continuous Challenges for Ultra-Low Power LSI - Technologies, and Their Impact to ITC Societies

Koichiro Ishibashi
IEICE Vietnam Section Lecture Meeting on ICT and Inauguration Ceremony
IEICE Vietnam Section Lecture
2013/03



78 国際会議プロシーディングス等

An On-Chip 250 mA 40 nm CMOS Digital LDO Using Dynamic Sampling Clock Frequency Scaling with Offset-Free TDC-Based Voltage Sensor

Kazuo Otsuga, Masafumi Onouchi, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita, Koichiro Ishibashi*, and Kazumasa Yanagisawa
25th IEEE International System-on-Chip Conference 2012
25th IEEE International System
2012/09



79 国際会議プロシーディングス等

Sleep Mode Implementation to ZigBee Router Devices for
Wireless Sensor Networks

Ryouta SHIRONO, VU Trong Thien, Kohichiro ISHIBASHI
ICDV 2012
ICDV 2012
2012/08



80 国際会議プロシーディングス等

Low Power Technologies and their impact on ITC Societies

石橋孝一郎
The 2011 International Conference on Integrated Circuits and Devices in Vietnam
The 2011 International Confere
2011



81 国際会議プロシーディングス等

A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process

Onouchi, M.; Otsuga, K.; Igarashi, Y.; Ikeya, T.; Morita, S.; Ishibashi, K.; Yanagisawa, K.
IEEE A-SSCC 2011
IEEE A-SSCC 2011
2011/11



82 国際会議プロシーディングス等

On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blockes with trimode power gating structure

K. Jinmyoung, T. Nakura, H. Takata, K. Ikeda, and K. Asada
37th European Solid-State Circuits Conference
37th European Solid-State Circ
2011/09



83 国際会議プロシーディングス等

Decoupling Capacitance Boosting for On-Chip
Resonant Supply Noise Reduction

Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeday and Kunihiro Asada
2011 IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
2011 IEEE 14th International S
2011/04



84 国際会議プロシーディングス等

LSI industry requirement to SOI for mobile applications

K. Ishibashi
the 3rd FDSOI Workshop
the 3rd FDSOI Workshop
2010



85 国際会議プロシーディングス等

Resonant supply noise canceller utilizing parasitic capacitance of sleep blocks

J. Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, K. Asada
VLSI Circuits symposium 2010
VLSI Circuits symposium 2010
2010



86 国際会議プロシーディングス等

A Low-Power Wide-Range Clock Synchronizer
with Predictive-Delay-Adjustment Scheme
for Continuous Voltage Scaling in DVFS Control

Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Yoshihiko Yasu, and Koichiro Ishibashi
A-SSCC 2009
A-SSCC 2009
2009



87 国際会議プロシーディングス等

Hot-CarrierAC Lifetime Enhancement due to Wire Resistance Effect (WRE) in 45nm CMOS Circuits

N. Mizuguchi, K. Takeuchi, H. Tobe, P. Lee and K. Ishibashi
SSDM2008
SSDM2008
2008



88 国際会議プロシーディングス等

Dynamic voltage boost (DVB) method for improving power integrity of low-power multi-processor SoCs

Y. Kanno, K. Yoshizumi, Y. Yasu, K. Ishibashi, H. Mizuno
VLSI Circuit Symposium
VLSI Circuit Symposium
2008



89 国際会議プロシーディングス等

Adaptive body bias techniques for low power SOC

K. Ishibashi
" in the special evening session” Chip Breakthroughs and Address Circuit/Device Interactions
" in the special evening sessi
2007



90 国際会議プロシーディングス等

Adaptive body bias techniques for low power SOC

K. Ishibashi
Microprocessor Forum
Microprocessor Forum
2007



91 国際会議プロシーディングス等

Adaptive Design of SRAM Memory Cells

K. Ishibashi
ISSCC 2007
ISSCC 2007
2007



92 国際会議プロシーディングス等

A 65-nm embedded SRAM with Wafer Level Burn-in Mode, Leak-bit Redundancy and E-trim Fuse for Known Good Die

S. Ohbayashi, M. Yabuuchi, Y. Oda, S. Imaoka, K. Usui, T. Yonezu, T. Iwamoto, K. Nii, Y. Tsukamoto, M. Arakawa, T. Uchida, M. Okada, A. Ishii, H. Makino, K. Ishibashi, and H. Shinohara
ISSCC 2007
ISSCC 2007
2007



93 国際会議プロシーディングス等

A 1.92μs-Wake-Up Time Thick-Gate-Oxide Power Switch Technique for Ultra Low-Power Single- Chip Mobile Processors

K. Fukuoka, O. Ozawa, R. Mori, Y. Igarashi, T. Sasaki, T. Kuraishi, Y. Yasu and K. Ishibashi
VLSI Circuit Symposium 2007
VLSI Circuit Symposium 2007
2007



94 国際会議プロシーディングス等

Adaptive Design of SRAM Memory Cells

K. Ishibashi
International Electron Devices Meeting
International Electron Devices
2007/12



95 国際会議プロシーディングス等

Adaptive body bias techniques for low power SOC

K. Ishibashi
International Solid-State Circuits Conference
International Solid-State Circ
2007/02



96 国際会議プロシーディングス等

A 65nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC

K. Nii, Y. Masuda, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, M. Igarashi, K. Tomita, N. Tsuboi, H. Makino, K. Ishibashi and H. Shinohara
VLSI Circuit Symposium 2006
VLSI Circuit Symposium 2006
2006



97 国際会議プロシーディングス等

A 65nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits

S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, M.Igarashi, M. Takeuchi, H. Kawashima, H. Makino, Y. Yamaguchi, K. Tsukamoto,M. Inuishi, H. Makino, K. Ishibashi and H. Shinohara
VLSI Circuit Symposimu 2006
VLSI Circuit Symposimu 2006
2006



98 国際会議プロシーディングス等

Low power SOC design using partial-trench-isolation ABC SOI (PTI-ABC SOI) for sub-100-nm LSTP technology

Osamu Ozawa, Kazuki Fukuoka, Yasuto Igarashi, Takashi Kuraishi, Yosihiko Yasu, Yukio Maki, Takashi Ipposhi, Toshihiko Ochiai, Masayoshi Shirahata, Koichiro Ishibashi
Symp. VLSI Circuits 2006
Symp. VLSI Circuits 2006
2006



99 国際会議プロシーディングス等

Circuit Technologies for Reducing the Power of SOC and Issues on Transistor Models

Koichiro Ishibashi, Shigeki Ohbayashi, Katsumi Eikyu, Motoaki Tanizawa, Yasumasa Tsukamoto, Kenichi Osada, Masayuki Miyazaki, and Masanao Yamaoka
International Electron Devices Meeting 2006 (IEDM 2006)
International Electron Devices
2006/12



100 国際会議プロシーディングス等

Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability

Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
ICCAD 2005
ICCAD 2005
2005



101 国際会議プロシーディングス等

0.5V asymmetric three-Tr. cell (ATC) DRAM using 90nm generic CMOS logic process

Motoi Ichihashi, Haruki Toda, Yasuo Itoh, Koichiro Ishibashi
Symp. VLSI Circuits 2005
Symp. VLSI Circuits 2005
2005



102 国際会議プロシーディングス等

An on-chip active decoupling circuit to suppress crosstalk in deep sub-micron CMOS mixed-signal SoCs

Toshiro Tsukada, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada, Koichiro Ishibashi
IEEE International Sold-State Circuits Conference
IEEE International Sold-State
2004



103 国際会議プロシーディングス等

A soft-error hardened latch scheme for SoC in a 90nm technology and beyond

Yoshihide Komatsu, Yukio Arima, Tetsuya Fujimoto, Takahiro Yamashita, Koichiro Ishibashi
2004 IEEE Custom Integrated Circuits Conference
2004 IEEE Custom Integrated Ci
2004



104 国際会議プロシーディングス等

Cosmic-ray immune latch circuit for 90nm technology and beyond

Yukio Arima, Takahiro Yamashita, Yoshihide Komatsu, Tetsuya Fujimoto, Koichiro Ishibashi
IEEE International Solid-State Circuits Conference
IEEE International Solid-State
2004/02



105 国際会議プロシーディングス等

Low Power Technology Development at STARC

Koichiro Ishibashi
The Second International Workshop on Nanoelectronics for Terra-bit Information Processing
The Second International Works
2004/01



106 国際会議プロシーディングス等

Low power SoC project at STARC: low voltage and high speed digital and analog circuits

K. Ishibashi
Seminar @IMEC
Seminar @IMEC
2003/11/07



107 国際会議プロシーディングス等

Low Power SoC Project in STARC

K. Ishibashi and T. Yamashita
2003 International Symp. on VLSI technology, Systems and Applications
2003 International Symp. on VL
2003/10



108 国際会議プロシーディングス等

Offset calibrating comparator array for 1.2-V, 6-bit, 4-Gsample/s flash ADCs using 0.13-um generic CMOS technology

Hiroyuki Okada, Yasuyuki Hashimoto, Kohji Sakata, Toshiro Tsukada, Koichiro Ishibashi
Proceedings of the 29th European Solid-State Circuits Conference
Proceedings of the 29th Europe
2003/09



109 国際会議プロシーディングス等

16.7fA/Cell tunnel-leakage-suppressed 16Mb SRAM for handling cosmic-ray-induced multi-errors

Kenichi Osada, Yoshikazu Saitoh, Eishi Ibe, Koichiro Ishibashi
IEEE International Sold-State Circits Conference
IEEE International Sold-State
2003/02



110 国際会議プロシーディングス等

A 9μW 50MHz 32b adder using a self-adjusted forward body bias in SoCs

Koichiro Ishibashi, Takahiro Yamashita, Yukio Arima, Isao Minematsu, Tetsuya Fujimoto
IEEE International Solid-State Circuits Conference
IEEE International Solid-State
2003/02



111 国際会議プロシーディングス等

A V-driver circuit for lowering power of sub-0.1/spl mu/m bus

Y. Arima, K. Ishibashi, T. Yamashita
2002 Asia-Pacific ASIC
2002 Asia-Pacific ASIC
2002



112 国際会議プロシーディングス等

0.4-V logic library friendly SRAM array using rectangular-diffusion cell and delta-boosted-array-voltage scheme

M. Yamaoka, K. Osada, and K. Ishibashi
2002 Symposium on VLSI Circuits
2002 Symposium on VLSI Circuit
2002



113 国際会議プロシーディングス等

Design rule for frequency-voltage cooperative power control and its application to an MPEG-4 decoder

K. Aisaka, T. Aritsuka, K. Ishibashi, H. Kawaguchi, S. Misaka, T. Sakurai, K. Toyama, K. Uchiyama
2002 Symposium on VLSI Circuits
2002 Symposium on VLSI Circuit
2002



114 国際会議プロシーディングス等

Substrate-Bias Techniques for SH4(未刊行論文)

K. Ishibashi
in the short course, 2001 VLSI Circuit Symposium
in the short course, 2001 VLSI
2001



115 国際会議プロシーディングス等

Low Power Memory

K. Ishibashi
in the short course, 2001 SSDM(International Symposium on Solid-State Devices and Materials)
in the short course, 2001 SSDM
2001



116 国際会議プロシーディングス等

A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit

M. Yamaoka, K. Yanagiwawa, S. Shukuri, K. Norisue, and K. Ishibashi
2001 Symposium on VLSI Circuits
2001 Symposium on VLSI Circuit
2001



117 国際会議プロシーディングス等

CMOS process compatible ie-Flash (inverse gate electrode Flash) technology for system-on-a-chip

K. Ishibashi, S. Shukuri, K. Tanagisawa
2001 CICC
2001 CICC
2001



118 国際会議プロシーディングス等

Universal-Vdd 0.65-2.0V 32 kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell

K. Osada, J. Shin, M. Khan, Y. Liou, K. Wang, K. Shoji, K. Kuroda, S. Ikeda and K. Ishibashi
2001 IEEE International Solid-state Circuits Conference
2001 IEEE International Solid-
2001



119 国際会議プロシーディングス等

CMOS process compatible ie-flash(inverse gate electrode flash) technology for system-on-a chip

Shoji Shukuri, Kazumasa Yanagisawa, Koichiro Ishibashi
2001 IEEE Custom Integrated Circuits Conference
2001 IEEE Custom Integrated Ci
2001/05



120 国際会議プロシーディングス等

Quantitative Study of SA-Vt CMOS Scheme Based on the Evaluation of Device Fluctuation

G. Ono, M. Miyazaki and K. Ishibashi
2000 International Conference on Solid State Devices and Materials
2000 International Conference
2000



121 国際会議プロシーディングス等

A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias

M. Miyazaki, G. Ono, T. Hattori, K. Shiozawa, K. Uchiyama, and K. Ishibashi
2000 IEEE International Solid-State Circuits Conference
2000 IEEE International Solid-
2000



122 国際会議プロシーディングス等

A 3-cycle lock time delay-locked loop with a parallel phase detector for low power mobile systems

M. Miyazaki and K. Ishibashi
AP-ASIC '99. The First IEEE Asia Pacific Conference
AP-ASIC '99. The First IEEE As
1999



123 国際会議プロシーディングス等

A 18 μA-standby-current 1.8 V 200 MHz microprocessor with self substrate-biased data-retention mode

H. Mizuno, K. Ishibashi, T. Shimura, T. Hattori, S. Narita, K. Shiozawa, S . Ikeda and K.Uchiyama
1999 IEEE International Solid-state Circuits Conference
1999 IEEE International Solid-
1999



124 国際会議プロシーディングス等

A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSls

M. Miyazaki, H. Mizuno, and K. Ishibashi
1998 International Symposium on Low Power Electronics and Design
1998 International Symposium o
1998



125 国際会議プロシーディングス等

A noise-immune GHz-clock distribution scheme using synchronous distributed oscillators

H. Mizuno and K. Ishibashi
1998 IEEE International Solid-state Circuits Conference
1998 IEEE International Solid-
1998



126 国際会議プロシーディングス等

A 200 MHz 1.2 W 1.4 GFLOPS microprocessor with graphic operation unit

O. Nishii, F. Arakawa, K. Ishibashi, S. Nakano, T. Shimura, K. Suzuki, M. Tachibana, . Totsuka, T. Tsunoda, K. Uchiyama, T. Yamada, T. Hattori, H. Maejima, N. Nakagawa, S. Narita, M. Seki, Y. Shimazaki, R. Satomura, T. Takasuga and A. Hasegawa
1998 IEEE International Solid-state Circuits Conference
1998 IEEE International Solid-
1998



127 国際会議プロシーディングス等

A Lean-power Gigascale LSI Using Hierarchical V/sub bb/ Routing Scheme With Frequency Adaptive V/sub t/ CMOS

H. Mizuno, M. Miyazaki, K. Ishibashi, Y. Nakagome, and T. Nagano
1997 Symposium on VLSI Circuits
1997 Symposium on VLSI Circuit
1997



128 国際会議プロシーディングス等

A Lean-power Gigascale LSI Using Hierarchical Vbb Routing Scheme With Frequency Adaptive Vt CMOS

K. Osada, H. Higuchi, K. Ishibashi, N. Hashimoto, K. Shiozawa
1997 IEEE International Solid-state Circuits Conference
1997 IEEE International Solid-
1997



129 国際会議プロシーディングス等

The Design Of 300MIPS Microprocessor With A Full Associative TLB For Hand-held PC OS

K. Ishibashi, H. Higuchi, Y. Shimbo, F. Arakawa, O. Nishii, N. Nakagawa, H. Maejima, K. Osada, K. Norisue, R. Satomura, H. Aoki, Y. Shimazaki, K. Tanaka, T. Hattori, K. Shiozawa, K. Kudo, K. Uchiyama, S. Narita, J. Nishimoto, T. Nagano, S. Ikeda, K. Kuroda, T. Takeda, and N. Hashimoto
1997 Symposium on VLSI Cirvuits
1997 Symposium on VLSI Cirvuit
1997



130 国際会議プロシーディングス等

A 1 V 100 MHz 10 mW cache using separated bit-line memory hierarchy and domino tag comparators

H. Mizuno, N. Matsuzaki, K. Osada
1996 IEEE International Solid-state Circuits Conference
1996 IEEE International Solid-
1996



131 国際会議プロシーディングス等

A cost-oriented two-port unified cache for low-power RISC microprocessors

H. Mizuno, N. Matsuzaki, K. Osada, T. Shinbo, N. Ohki, H. Ishida, K . Ishibashi and T.Kure
1996 Symposium on VLSI Circuits
1996 Symposium on VLSI Circuit
1996



132 国際会議プロシーディングス等

A 6.93-μm2 n-gate full CMOS SRAM cell technology with high-performance 1.8-V dual-gate CMOS for peripheral circuits

M. Minami, N. OhkiH. Ishida, T. Yamanaka, A. Shimizu, K. Ishibashi, A. Satoh, T. Kure, T. Nishida, and T. Nagano
1995 Symposium on VLSI Technology
1995 Symposium on VLSI Technol
1995



133 国際会議プロシーディングス等

An automatic-power-save cache memory for low-power RISC processors

Y. Shimazaki, K. Ishibashi, K. Norisue, S. Narita, K. Uchiyama, T. Nakazawa, I. Kudoh, R. Izawa, S. Yoshioka, S. Tamaki, S. Nagata, I. Kawasaki, K. Kuroda
IEEE Symposium on Low Power Electronics and Design 1995
IEEE Symposium on Low Power El
1995



134 国際会議プロシーディングス等

A low-power single-chip microprocessor with multiple page-size MMU for nomadic computing

S. Narita, K. Ishibashi, S. Tachibana, K. Norisue, Y. Shimazaki, J. Nishimoto, K. Uchiyama, T. Nakazawa, K. Hirose, I. Kudoh, R. Izawa, S. Matsui, S. Yoshioka, M. Yamamoto, I. Kawasaki
1995 Symposium on VLSI Circuits
1995 Symposium on VLSI Circuit
1995



135 国際会議プロシーディングス等

A 300 MHz 4-Mb wave-pipeline CMOS SRAM using a multi-phase PLL

K. Ishibashi, K. Komiyaji, H. Toyoshima, R. Minami, N. Ohki, H. Ishida, T. Yamanaka,T .Nagano, and T. Nishida
1995 IEEE International Solid-state Circuits Conference
1995 IEEE International Solid-
1995



136 国際会議プロシーディングス等

A 6-ns 4-mb Cmos Sram With Offset-voltage-insensitive Current Sense Amplifiers

K. Ishibashi, K. Takasugi, K. Komiyaji, H. Toyoshima, T. Yamanaka, A . Fuk ami, N.Hashimoto, N. Ohki, A. Shimizu, T. Hashimoto, T. Nagano and T. Nishida
1994 Symoposium on VLSI Circuits
1994 Symoposium on VLSI Circui
1994



137 国際会議プロシーディングス等

A 12.5ns 16Mb CMOS SRAM

K. Ishibashi, K. Takasugi, T. Hashimoto and K. Sasaki
1993 Symposium on VLSI Circuits
1993 Symposium on VLSI Circuit
1993



138 国際会議プロシーディングス等

A stacked split word-line (SSW) cell for low-voltage operation, large capacity, high speed SRAMs

Shuji Ikeda, Kyoichiro Asayama, Naotaka Hashimoto, Eri Fujita, Yasuko Yoshida, Atsuyosi Koike, Toshiaki Yamanaka, Koichiro Ishibashi, Satoshi Meguro
IEDM Tech. Dig.
IEDM Tech. Dig.
1993/12



139 国際会議プロシーディングス等

A 7 ns 140 mW 1 Mb CMOS SRAM with current sense amplifier

K. Sasaki, K. Ishibashi, K. Ueda, K. Komiyaji, T. Yamanaka, N.Hashimoto, H.T oyos him a,F .Kojima and A. Shimizu
1992 IEEE International Solid-state Circuits Conference
1992 IEEE International Solid-
1992



140 国際会議プロシーディングス等

A 1 V TFT-load SRAM using a two-step word-voltage method

K. Ishibashi, K. Takasugi, T. Hashimoto and K. Sasaki
1992 IEEE International Solid-state Circuits Conference
1992 IEEE International Solid-
1992



141 国際会議プロシーディングス等

Low power, low voltage memories for portable electronics

O. Minato, K. Ishibashi
1991 International Symposium on Technology, Systems and Applications
1991 International Symposium o
1991



142 国際会議プロシーディングス等

A 1.7V Adjustable I/O Interface for Low Voltage Fast SRAMs

K. Ishibashi, K. Sasaki, T. Yamanaka, H. Toyoshima, and F. Kojima
1991 Symposium on VLSI Circuits
1991 Symposium on VLSI Circuit
1991



143 国際会議プロシーディングス等

A 5.9 μm2 super low power SRAM cell using a new phase-shift lithography

T. Yamanaka, N. Hasegawa, T. Tanaka, K. Ishibashi, T. Hashimoto, A. Shimizu, N. Hashimoto, K. Sasaki, T. Nishida, and E. Takeda
1990 International Electron Devices Meeting
1990 International Electron De
1990



144 国際会議プロシーディングス等

A 23 ns 4 Mb CMOS SRAM with 0.5 μA standby current

K. Sasaki, K. Ishibashi, T. Yamanaka, K. Shimohigashi, N. Moriwaki, S. Honjo, S. Ikeda, A Koike, S, Meguro and O. Minato
1990 IEEE International Solic-state Circuits Conference
1990 IEEE International Solic-
1990



145 国際会議プロシーディングス等

A 9 ns 1 Mb CMOS SRAM

K. Sasaki, S. Hanamura, K. Ishibashi, T. Yamanaka, N. Hashimoto, T. Nishida, K. Shimohigashi, and S. Honjo
1989 IEEE International Solid-state Circuits Conference
1989 IEEE International Solid-
1989



146 国際会議プロシーディングス等

An alpha-immune, 2V supply voltage SRAM using polysilicon PMOS load cell

K. Ishibashi, T. Yamanaka and K. Shimohigashi
1989 Symposium on VLSI Circuits
1989 Symposium on VLSI Circuit
1989



147 国際会議プロシーディングス等

A 25 μm2, new poly-Si PMOS load (PPL) SRAM cell having excellent soft error immunity

T. Yamanaka, T. Hashimoto, N. Hashimoto, T. Nishida, A. Shimuzu, K. Ishibashi, Y. Sakai, K. Shimohigashi, E. Takeda
Electron Devices Meeting., Technical Digest., International
Electron Devices Meeting., Tec
1988



148 国際会議プロシーディングス等

A 42ns 1Mb CMOS SRAM

O. Minato, T. Sasaki, S. Honjo, K. Ishibashi, Y. Sasaki, N. Moriwaki, K. Nishimura, Y. Sakai, S. Meguro, M. Tsunematsu, and T. Masuhara
1987 IEEE International Solid-state Circuits Conference
1987 IEEE International Solid-
1987



149 国際会議プロシーディングス等

Formation of SPE-CoSi2 Submicron Line by Lift Off Using Selective Reaction

K. Ishibashi and S. Furukawa
1984 Internaitonal Conference on Solid-state Devices and Materials
1984 Internaitonal Conference
1984



150 国際会議プロシーディングス等

Si permeable base transistor by metal/semiconductor hetero-epitaxy

K. Ishibashi and S. Furukawa
1984 International Electron Devices Meeting
1984 International Electron De
1984



151 国際会議プロシーディングス等

Study on Formation of Solid-Phase-Epitaxial CoSi2 Films and Patterning Effects

K. Ishibashi, H. Ishiwara, and S. Furukawa
1983 International Conference on Solid-state Devices and Materials
1983 International Conference
1983



152 解説

増大するプロセッサの消費電力(2) - 基板バイアス技術を採用

石橋孝一郎
Web 雑誌 マイコミジャーナル
2003/4/4-
2003/04



153 解説

増大するプロセッサの消費電力(1) - 省電力化のセオリーとは

石橋孝一郎
Web 雑誌 マイコミジャーナル
2003/4/4-
2003/04