| No. |
種別 |
査読の有無 |
標題 |
単著・共著区分 |
著者 |
誌名 |
巻号頁 |
出版日 |
ISSN |
DOI |
URL |
| 1 |
一般論文
|
有
|
Footprint-Based DIMM Hotplug
|
共著
|
S. Miwa, M. Ishihara, H. Yamaki, H. Honda, and M. Schulz
|
IEEE Transactions on Computers
|
69/ 2, 172-184
|
2020/02
|
|
|
|
| 2 |
一般論文
|
有
|
Flow-Length Aware Cache Replacement Policy for Packet Processing Cache
|
単著
|
H. Yamaki
|
International Journal of Advanced Computer Science and Applications (IJACSA)
|
9/ 5, 12-20
|
2018/06/01
|
2158-107X
|
|
|
| 3 |
一般論文
|
有
|
インターネットルータにおけるHTTP圧縮ストリームの高速展開処理機構の提案
|
共著
|
八巻隼人、中村優一、高際健一、松井加奈絵、西宏章
|
電子情報通信学会論文誌B
|
J98-B/ 10, 1104-1114
|
2015/10/01
|
|
|
|
| 4 |
一般論文
|
有
|
An Improved Cache Mechanism for a Cache-based Network Processor
|
共著
|
H. Yamaki, H. Nishi
|
Journal of Communication and Computer
|
10/ 3, 277-286
|
2013/03/01
|
|
|
|
| 5 |
一般論文
|
有
|
Effective Hash-Based Filtering Architecture for High-throughput Regular-Expression Matching
|
共著
|
H. Yamaki, Y. Nagatomi, and H. Nishi
|
International Journal of Information and Electronics Engineering
|
2/ 5, 672-677
|
2012/09/01
|
|
|
|
| 6 |
国際会議プロシーディングス等
|
有
|
Efficient Cache Architecture for Packet Processing in Internet Routers
|
単著
|
H. Yamaki
|
Proceedings of the 2020 Future of Information and Communication Conference (FICC)
|
1, 338-352
|
2020/03
|
|
|
|
| 7 |
国際会議プロシーディングス等
|
有
|
Functionally-Predefined Kernel: a Way to Reduce CNN Computation
|
共著
|
Y. Inouchi, H. Yamaki, S. Miwa, and T. Tsumura
|
The 2019 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PacRim 2019)
|
1-6
|
2019/08
|
|
|
|
| 8 |
国際会議プロシーディングス等
|
有
|
Multi-Level Packet Processing Caches
|
共著
|
K. Tanaka, H. Yamaki, S. Miwa, and H. Honda
|
The 2019 IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 22)
|
1-3
|
2019/04
|
|
|
|
| 9 |
国際会議プロシーディングス等
|
有
|
Optimizing Memory Hierarchy within an Internet Router for High-Throughput and Energy-Efficient Packet Processing
|
共著
|
K. Tanaka, H. Yamaki, S. Miwa, and H. Honda
|
ACM Student Research Competition (in conjunction with the 51st Annual ACM/IEEE International Symposium on Microarchitecture) (poster presentation)
|
poster
|
2018
|
|
|
|
| 10 |
国際会議プロシーディングス等
|
有
|
Data Prediction for Response Flows in Packet Processing Cache
|
共著
|
Hayato Yamaki, Hiroaki Nishi, Shinobu Miwa, Hiroki Honda
|
Proceedings of the 55th Annual Design Automation Conference (DAC '18)
|
110, 1-6
|
2018/06/24
|
|
|
|
| 11 |
国際会議プロシーディングス等
|
有
|
Flow Characteristic-Aware Cache Replacement Policy for Packet Processing Cache
|
単著
|
H. Yamaki
|
In Proceedings of Future of Information and Communication Conference (FICC 2018)
|
1-8
|
2018/04/05
|
|
|
|
| 12 |
国際会議プロシーディングス等
|
有
|
Initial Study of Reconfigurable Neural Network Accelerators
|
共著
|
Momoka Ohba, Satoshi Shindo, Shinobu Miwa, Tomoaki Tsumura, Hayato Yamaki, and Hiroki Honda
|
7th International Workshop on Advances in Networking and Computing (WANC'16)
|
1, 707-709
|
2016/11
|
|
|
|
| 13 |
国際会議プロシーディングス等
|
有
|
Line Replacement Algorithm for L1-scale Packet Processing Cache
|
共著
|
H. Yamaki, H. Nishi
|
In Adjunct Proceedings of 13th Annual International Conference on Mobile and Ubiquitous Systems: Computing, Networking and Services (MOBIQUITOUS'16)
|
12-17
|
2016/11/28
|
|
|
|
| 14 |
国際会議プロシーディングス等
|
有
|
High-Speed Decompression Architecture of Compressed HTTP Streams for the Internet Routers
|
|
H. Okano, H. Yamaki, H. Nishi
|
Proceedings of The International Conference on FPGA Reconfiguration for General-Purpose Computing (FPGA4GPC)
|
25-30
|
2016/05/09
|
|
|
|
| 15 |
国際会議プロシーディングス等
|
有
|
An Improved Cache Mechanism for a Cache-based Network Processor
|
共著
|
H. Yamaki, H. Nishi
|
Proceedings of The 2012 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA2012 in WORLDCOMP2012)
|
428-434
|
2012/07/17
|
|
|
|