Published papers
Number of published data : 14
No. Classification Refereed paper Title Authorship Author Journal Volume/issue/page Publication date ISSN DOI URL
1 Paper
Yes
Asymmetric Leakage from Multiplier and Collision-Based Single-Shot Side-Channel Attack
Joint
T. Sugawara, D. Suzuki, and M. Saeki
IEICE Trans. Fundamentals
E99-A/ 7, 1323-1333
2017/07



2 Paper
Yes
Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication
Joint
K. Shimizu, D. Suzuki, T. Tsurumaru, T. Sugawara, M. Shiozaki, and T. Fujino
IEICE Trans. Fundamentals
97-A/ 1, 264-274
2014/01



3 Paper
Yes
Evaluation of Information Leakage from Cryptographic Hardware via Common-Mode Current

Y. Hayashi, N. Homma, T. Mizuki, T. Sugawara, Y. Kayano, T. Aoki, S. Minegishi, A. Satoh, H. Sone, and H. Inoue
IEICE Trans. Electronics
E95-C/ 6, 1089-1097
2012/06



4 Paper
Yes
Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates
Joint
M. Knezevic, K. Kobayashi, J. Ikegami, S. Matsuo, A. Satoh, U. Kocabas, J. Fan, T. Katashita, T. Sugawara, K. Sakiyama, I. Verbauwhede, K. Ohta, N. Homma, and T. Aoki
IEEE Trans. VLSI Syst.
20/ 5, 827-840
2012/05



5 Paper
Yes
A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments

S. Endo, T. Sugawara, N. Homma, T. Aoki, and A. Satoh
IEICE Trans, Fundamentals
95-A/ 1, 263-266
2012/01



6 Paper
Yes
An On-chip Glitchy-clock Generator for Testing Fault Injection Attacks
Joint
S. Endo, T. Sugawara, N. Homma, T. Aoki, and A. Satoh
Journal of Cryptographic Engineering
1/ 4, 265-270
2011/12



7 Paper
Yes
ハッシュ関数Luffaのハードウェア実装
Joint
片下敏宏, 佐藤証, 菅原健, 本間尚文, 佐藤証, 青木孝文
情報処理学会論文誌
52/ 12, 3755-3765
2011/12



8 Paper
Yes
High-performance Architecture for Concurrent Error Detection for AES Processors
Joint
T. Sugawara, N. Homma, T. Aoki, and A. Satoh
IEICE Trans. Fundamentals
E94-A/ 10, 1971-1980
2011/10



9 Paper
Yes
Profiling Attack using Multivariate Regression Analysis
Joint
T. Sugawara, N. Homma, T. Aoki, and A. Satoh
IEICE Electronics Express
7/ 15, 1139-1144
2010/08



10 Paper
Yes
ハッシュ関数Whirlpoolの高スケーラブル回路アーキテクチャ
Joint
菅原健, 本間尚文, 佐藤証,青木孝文
情報処理学会論文誌
50/ 11, 2618-2632
2009/11



11 Paper
Yes
High-Performance Hardware Architectures for Galois Counter Mode
Joint
A. Satoh, T. Sugawara, and T. Aoki
IEEE Trans. Computers
58/ 7, 917-930
2009/07



12 Paper
Yes
A High-Resolution Phase-Based Waveform Matching and Its Application to Side-Channel Attacks
Joint
N. Homma, S. Nagashima, T. Sugawara, T. Aoki, and A. Satoh
IEICE Trans. Fundamentals
E91-A/ 1, 193-202
2008/01



13 Invited paper
Yes
Reversing stealthy dopant-level circuits
Joint
T. Sugawara, D. Suzuki, R. Fujii, S. Tawa, R. Hori, M. Shiozaki, and T. Fujino
Journal of Cryptographic Engineering
5/ 2, 85-94
2015/07



14 Invited paper
Yes
On measurable side-channel leaks inside ASIC design primitives
Joint
T. Sugawara, D. Suzuki, M. Saeki, M. Shiozaki, and T. Fujino
Journal of Cryptographic Engineering
4/ 1, 59-73
2014/04